Hillsboro, Ore.—Lattice Semiconductor Corp. has released the LatticeECP2M FPGA family, consisting of low cost devices that offer high-speed embedded SerDes I/O plus a pre-engineered Physical Coding ...
SUWANEE, Ga.--(BUSINESS WIRE)--Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced that its multi-protocol serializer/deserializer ...
Two core products, the 10 Gigabit Physical Coding Sublayer (PCS) and the Media Access Controller (MAC), are intended for use in Xilinx’s Virtex-II and Virtex-II Pro field programmable gate arrays ...
Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations. Gliwice & Bielsko-Biala, Poland, June ...
Synopsys has released the first 1.6T Ethernet IP verification solution to meet the bandwidth demands of hyperscale data centers. The new multi-channel, multi-rate solutions include 1.6T MAC (Media ...
Synopsys completed its acquisition of MorethanIP, a provider of Ethernet Digital Controller IP supporting data rates from 10G to 800G. The acquisition adds MAC (Medium Access Controller) and PCS ...
Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include ...
Belgrade, Serbia – March 12th, 2013 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced availability of its Physical ...
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